1. Field of the Invention
The present invention relates to a system and method for fabricating a semiconductor device and an isolation structure thereof, and in particular to an improved system and method for fabricating a semiconductor device and an isolation structure thereof which are capable of overcoming problems such as a rounded corner portion problem, a pattern length decrease, etc. and enhancing the integrity of the semiconductor device.
2. Description of the Background Art
Generally, when fabricating a semiconductor device, a semiconductor substrate is divided into an active region in which a semiconductor device is formed and a non-active region that is electrically isolated from the active region. Through this division, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) may be fabricated.
FIG. 1 illustrates a semiconductor substrate having an active region 2 and a non-active region 3 for fabricating a conventional DRAM (Dynamic Random Access Memory) cell among the semiconductor devices. In the drawings, reference numeral 2 represents the active region 2 on the semiconductor substrate 100 which is shown by a full line, and a reference numeral 2' represents a pattern of an ideal (desired) active region which is shown by a dotted line. The region around the active region 2 is a non-active region 3.
FIGS. 2A through 2D illustrate a process for fabricating the active region 2 and the non-active region 3 of FIG. 1, namely, the isolation structure fabrication process for a semiconductor device.
As shown therein, a first insulation film 101 and a second insulation film 102 are formed on the semiconductor substrate 100. Generally, the first insulation film 101 is formed of an oxide film, and the second insulation film 102 is formed of a nitride film. A photoresist pattern 103 corresponding to the active region is formed on the second insulation film 102. At this time, the photoresist pattern 103 is formed of an island shape pattern like the active region pattern 2' of FIG. 1.
As shown in FIG. 2B, the second insulation film 102 and the first insulation film 101 are etched using the photoresist pattern 103 as a mask. Thereafter, the semiconductor substrate 100 formed on the portion in which the first insulation film 101 is removed by etching to a predetermined thickness, thereby forming a shallow trench 104.
As shown in FIG. 2C, a third insulation film (oxide film) 105 is filled into the shallow trench 104. The upper surface of the semiconductor substrate 100 is planerized by a planerizing process. FIG. 2D is a cross-sectional view taken along the line IId--IId of FIG. 2C. In the drawings, reference numeral 3 represents a device isolation region(non-active region) filled by the third insulation film 105, and reference numeral 2 represents an active region. As shown in FIG. 2C, the active region 2 is not a rectangular shape region but a corner-rounded rectangular shape region. Namely, the corner portions of the photoresist pattern 103 are rounded when forming the photoresist pattern 103 during a light exposing process. Therefore, since the semiconductor substrate 100 is etched using the photoresist pattern 103 as a mask, the corner portions of the active region 2 are rounded.
In the above-described process, instead of the process in which the shallow trench 104 is formed, the LOCOS (Local Oxidation of silicon) may be processed for etching the nitride and oxide films using the photoresist pattern 13 as a mask, oxidizing the exposed semiconductor substrate and forming a thick oxide film (field oxide film).
FIG. 3A illustrates a semiconductor substrate after the MOSFET is formed on the semiconductor substrate 100 of FIG. 2D, after the above-described device isolation process is completed. Namely, the gate insulation film and the conductive layer are formed on the semiconductor substrate 100 of FIG. 2D and subsequently are patterned to form a gate electrode 5 as a word line, which extends in a direction perpendicular to a direction along the length L of the active region 2. A dopant is implanted into the active region 2 of the gate electrode 5 to form the source 6 and the drain 6 for thus fabricating the MOSFET which is the semiconductor device.
FIG. 3B is a vertical cross-sectional view taken along the line IIIb--IIIb of FIG. 3A. The reference numerals of FIG. 3B correspond to the reference numerals of the elements of FIG. 3A.
The problems of the fabrication method for a known semiconductor device isolation structure fabrication method will be explained with reference to FIGS. 1 and 2A through 2D.
As shown in FIG. 1, a plurality of active regions 2 are formed like islands on the semiconductor substrate 1, and selectively isolated by the non-active region 3. In FIG. 1, the rectangular region 2' indicated by the dotted line is an ideal active region pattern 1. However, the active region 2 formed on the semiconductor substrate using the rectangular active region pattern 2' is rounded in its corner portions. Namely, the corner portions of the active region 2 formed on the semiconductor substrate are rounded based on the photolithography and etching processes that are performed based on a rectangular active region pattern. In addition, the length L of the active region 2 becomes smaller than the length L' of the ideal active region pattern 2' due to the lens distortion problem, optical adjacent effect, etc. Therefore, when forming a wire connection contact hole at the end portions at both sides of the active region, the fabrication margin may be decreased, and when the position alignment accuracy is decreased when forming the contact hole, a connection error may occur between the wiring portion and the active region, thereby decreasing a reliability of the semiconductor device and production yield.
When the distance between adjacent active region patterns 2 is short in the direction of the width W of the active region pattern 2 of FIG. 1, the adjacent active region patterns 2 may be unintentionally combined into one active pattern, causing a short circuit in the semiconductor device formed using the active region pattern 2'. To overcome the above-described problems, a substantial distance has been formed between the active region pattern 2 and the active region pattern 2', causing a decrease in the number of devices integrated on the semiconductor substrate, thereby decreasing the integration characteristic of the semiconductor devices.